1. Field
Example embodiments relate generally to semiconductor memory devices and a method thereof.
2. Description of the Related Art
Conventional non-volatile memory devices may include mask read only memory (ROM), electrically erasable and programmable ROM (EEPROM), and erasable and programmable ROM (EPROM). Flash EEPROM (hereinafter, referred to as a “flash memory device”) may have a relatively high degree of integration as compared to other EEPROMs. Flash memory devices may include NAND flash memory devices, NOR flash memory devices and AND flash memory devices. NAND flash memory devices have a relatively high degree of integration and may be used for storing data. NOR flash memory devices may have a relatively fast data access speed and may be for storing program codes.
FIG. 1 illustrates a conventional semiconductor memory device 10 including a sense amplifier. Referring to FIG. 1, the semiconductor memory device 10 (e.g., a NOR flash memory device) may include a plurality of memory banks 20, 30 and 40, a plurality of control signal generators 21, 25, 31, 35, 41, and 45, a plurality of sense amplifier banks 23, 27, 33, 37, 43, and 47, a first reference cell group 50 and a second reference cell group 60.
Referring to FIG. 1, the first memory bank 20 may include at least one memory cell. The first control signal generator 21 may generate a first control signal REF0 in response to a first reference current Ir1 flowing in the first reference cell group 50. The at least one memory cell may be implemented by flash EEPROM.
Referring to FIG. 1, the first sense amplifier bank 23 may include at least one first sense amplifier (not shown). The first sense amplifier may sense data stored in a first memory cell (not shown) included in the first memory bank 20 based on a first current, which may flow in a first bit line (not shown) connected with the first memory cell, and a second current, which may be generated in response to the first control signal REF0.
Referring to FIG. 1, a magnitude of the second current may depend on a swing width of the first control signal REF0. If the first current is greater than the second current, the first sense amplifier may output a first logic level (e.g., a higher logic level or logic “1”). If the first current is not greater than the second current, the first sense amplifier may output a second logic level (e.g., a lower logic level or logic “0”).
Referring to FIG. 1, the second control signal generator 25 may generate a second control signal REF1 in response to a second reference current Ir2 flowing in the second reference cell group 60. The second sense amplifier bank 27 may include at least one second sense amplifier (not shown). The second sense amplifier may sense data stored in a second memory cell (not shown) included in the first memory bank 20 based on a third current, which may flow in a second bit line (not shown) connected with the second memory cell, and a fourth current, which may be generated in response to the second control signal REF1.
Referring to FIG. 1, a magnitude of the fourth current may depend on a swing width of the second control signal REF1. If the fourth current is greater than the third current, the second sense amplifier may output the first logic level (e.g., a higher logic level or logic “1”). If the fourth current is not greater than the third current, the second sense amplifier may output the second logic level (e.g., a lower logic level or logic “0”).
Referring to FIG. 1, the first reference cell group 50 may include at least one memory cell including a source, a drain, a floating gate, a control gate, and a substrate. The first reference cell group 50 may generate the first reference current Ir1 in response to a reference current generation signal Ref. The second reference cell group 60 may include at least one memory cell including a source, a drain, a floating gate, a control gate, and a substrate. The second reference cell group 60 may generate the second reference current Ir2 in response to the reference current generation signal Ref.
Referring to FIG. 1, if the magnitude of the first reference current Ir1 is equal to that of the second reference current Ir2, the first control signal REF0 may be the same as the second control signal REF1 and currents (e.g., the second current and the fourth current), which may be respectively used as references if data in memory cells (e.g., the first memory cell and the second memory cell) are sensed, may likewise be the same.
However, if the magnitudes of the first and second reference currents Ir1 and Ir2 are not equal to each other, the first control signal REF0 may not be the same as the second control signal REF1 and the currents, which may be respectively used as references if data in the memory cells are sensed, may not necessarily be the same. Accordingly, data stored in the memory cells may not be reliably or consistently sensed.
For example, the first control signal REF0 and the second control signal REF1 may be generated based on currents flowing in different reference cells (e.g., the first reference cell group 50 and the second reference cell group 60), respectively, and therefore, it may be difficult to match the first control signal REF0 and the second control signal REF1. In addition, the first control signal REF0 input to a sense amplifier, which may be positioned relatively far away from the first control signal generator 21 among a plurality of sense amplifiers included in the first sense amplifier bank 23, may be distorted, and therefore, data stored in memory cells may not be reliably sensed.
In another example, because multi-level cell (MLC) flash memory may have a relatively small read margin, matching between reference currents generated in different reference cells may be an important design criterion. For example, each of memory cells in the MLC flash memory may identify one of four data states (e.g., “11”, “10”, “01”, and “00”) based on a reference current during a data read operation, and therefore, data sensing of memory cells may relatively unreliable if the reference currents of the memory cells are not substantially the same during the data sensing.